Dynamic verification via simulation of Very Large Scale Integration (VLSI) chips is one of the most time-consuming steps of VLSI design. Increasing the speed at which simulation is performed can greatly reduce the cycle-time for designing VLSI chips. It also allows for more extensive testing, resulting in more reliable chips. Reducing the memory consumption required during these simulations makes it is possible to run simulations on all low-end computers, and to run multiple simulations on the same computer. This allows designers to exploit all plant wide computing resources. Running multiple simulations in parallel allows more simulation cycles to be run per unit time.
The Verilog Hardware Description Language (Verilog) is a hardware description language in common use for specifying Integrated Circuit (IC) designs for use in testing such IC designs through simulation testing. Verilog describes a hardware design or part of a design. Descriptions of designs in Verilog are Verilog Models. Verilog is both a behavioral and a structural language. Verilog Models can describe both the functionality of a design and the components and connections to the components in a design.
Verilog-XL from Cadence Design Systems is commonly used to interpret Verilog code. Unfortunately, Verilog-XL is quite slow interpreting Verilog. The result of this slowness has been that IC designers have not been able to do as much testing as might seem desirable.